1. Field of the Invention
The present invention relates to an integrated gate drive controller for synchronous rectifiers. More specifically, the present invention relates to an integrated gate drive controller for synchronous rectifiers that minimizes secondary side stray inductance effects by controlling overlap of the gate drive signals.
2. Brief Description of the Related Art
The use of power MOSFETs as synchronous rectifiers in DC/DC converters with isolated buck topology derivatives is well known. Power MOSFETs result in higher efficiency systems due to lower losses offered by their on-resistance. The recent trends towards lower output voltages and higher currents have made the power MOSFET a highly desirable option for rectification in the secondary side of such converters.
In order for power MOSFETs to operate properly in these topologies, an appropriate gate drive is necessary. By far, the most widely used method for generating the gate drive is the cross-coupled or self-driven scheme. An alternative arrangement is to connect the MOSFET as so-called two terminal switches. These and other known arrangements are shown and described in U.S. Pat. No. 6,026,005, issued to the present inventor and incorporated in its entirety herein by reference.
The power converter disclosed in U.S. Pat. No. 6,026,005 includes a modified PLL with an adjustable delay block in the feedback path that forces the VCO output signal to lead the input signal. One drawback that is not addressed by the power converter of U.S. Pat. No. 6,026,005 is the effect of stray inductances in the secondary side. These stray inductances are disadvantagous in that they maintain a current flow even if the MOSFETs with which they are associated have zero tun-on/off times. This results in MOSFET body diode conduction and unnecessary losses until the current dissipates.
It would be beneficial to provide a controller which minimizes the effects of secondary side stray inductance.
The present invention overcomes the deficiencies of the prior art, such as those noted above, by providing synchronous rectifier circuit driver that controls dead time/overlap of the rectifier transistor gates.
According to a preferred embodiment, a switching power converter includes a switching transformer having a primary winding and a secondary winding. The secondary winding has first and second voltage nodes across which a winding voltage having a phase and a variable duty cycle is impressed. A first synchronous rectifier transistor is coupled from the first voltage node to a common node, and a second synchronous rectifier transistor is coupled from the second voltage node to the common node. A driver circuit receives the winding voltage and produces first and second drive signals to the first and second synchronous rectifier transistors, respectively. The driver circuit is operable to maintain both transistors on at the same time for a short period, such that induction currents are allowed to dissipate through the transistors rather than the transistor body diode. Accordingly, conduction losses are reduced.
In particular, dead time/overlap control is provided by a pair of NOR latches having inputs and outputs interconnected. As a result, the output gate drives will cross at approximately 50% of Vdd. For a 5 VDC supply, this will translate into 2.5 VDC which constitutes a slight overlap for logic level gate drives with Vth=1.7 Vdc. Addition of resistors and capacitors will reduce the crossover point from xc2xd Vdd and result in a dead time (no overlap) between the turn-off of one synchronous rectifier device and the turn-on of the other.
In a particularly preferred embodiment, both overlap and dead time of gate drives are used in the same converter circuit at different switching cycles. In topologies using a simple diode to reset the transformer, overlap is used at the transition from the reset cycle to the power transfer cycle. At this transition, the transformer is already reset (Vout(Tx)=0) and there is no danger of causing a cross conduction current. At the power transfer to reset cycle transition, a slight amount of dead time is used to prevent cross conduction. This is required due to the latency of the transformer turn off (due to stray magnetizing inductance, capacitance and/or stray inductance of the transformer). The amount of dead time is primarily dictated by circuit parasitics.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.